The present invention relates to packages for electrical circuits, and in particular to such packages, and to a method for manufacturing same, which encapsulate an electrical circuit within a self-contained volume.
Applications in which electrical, optical, micromechanical or other devices may be arranged within a package to ensure their functioning are manifold. For example, infrared sensors for infrared cameras, thermal image cameras or image sensors for night-vision devices are arranged within closed packages for avoiding damage or environmental factors distorting the measurements. In the micromechanical field, this is also true for gyroscopes and electrically adjustable micro-mirrors and other mechanical components such as micromechanical sensors. In cameras for visible light or other sensors, both individual sensors, rows of sensors or entire two-dimensional arrays may be arranged within a package in this context.
With some sensors such as bolometers, for example, the requirements placed upon the package are extremely high if same has to enclose the sensor, however without impairing the sensor's functionality in that the quantity to be measured by the sensor is distorted by the package. For a bolometer, which essentially serves to measure temperatures by detecting emitted infrared radiation, packages are particularly complicated to manufacture, as will be briefly explained below.
A bolometer as is shown in FIG. 6, for example, measures the infrared radiation essentially in that the radiation is absorbed within a material which is arranged within the sensor and whose temperature and resistance changes as a result. Such a membrane 2, which consists of a material having a finite electrical resistance, will change this resistance as a function of the increase in temperature and of the temperature coefficient of the resistance. However, this gives rise to the problem that the temperature change in the resistance is very small (several Millikelvin) due to the small amount of incoming energy of the thermal radiation in the infrared range. It is therefore particularly important, in the bolometer shown in FIG. 6, to arrange the membrane 2 such that it is thermally isolated from a carrier substrate 4 so as not to influence the extremely sensitive measurement, for example in that the membrane temperature is artificially modified by being thermally conducted via the connection contacts of the membrane 2. Thus, the success of the measurement highly depends on that the resistor is mounted such that its thermal isolation is good. This is generally achieved in that the membrane 2 is connected to the substrate via connections 6a and 6b comprising thin, long arms, as may be seen in FIG. 6. These arms exhibit a relatively high thermal resistance, since their heat-transferring cross-section is very small.
Since on such an integrated device, the large-area membrane 2 is arranged at a small distance from the substrate 4, the thermal conduction occurring via the gap between the membrane 2 and the substrate 4 may be undermined. Since the most efficient heat transfer occurs by convection, the surroundings of the bolometer and/or of the membrane 2 may be evacuated. Conventionally, this has generally been realized in that the microbolometer chip as such is mounted within a package which may be evacuated. FIGS. 7 and 8 depict an example of such a package which is in line with conventional technology, the exploded view in FIG. 7 in particular showing how much effort is involved in manufacturing such a package. Such packages, which are typically made of metal, are consequently very costly, so that they are not suitable for being used in the mass market. Moreover, due to the fact that the entire chip is fully enclosed by the package, the volume of the package is clearly larger than that of the actual detector chip.
Therefore, in the recent past an enormous amount of effort has been put into developing methods which enable packaging a device as early as at the wafer level.
For example, U.S. Pat. No. 5,895,233 describes how a package may be fabricated which is hardly any larger than the detector chip itself. In this context, microbolometer arrays are manufactured on a substrate, or on a first wafer. Each array has a metal frame manufactured around it, on which soldering tin is deposited. A lid wafer is manufactured which is also provided with a plurality of solderable metal frames. The arrangement of the frames on the second wafer matches, as a mirror image, the frames on the first wafer. In a wafer bonding process, the lid wafer is initially mounted upside down on the substrate wafer, each frame of the lid wafer coming to lie on the corresponding frame of the substrate wafer. Subsequently, both wafers are soldered to each other under protective gas or under vacuum. For singulating, or dicing, the chips, the resulting layer structure is subsequently sawn into pieces and disassembled into the individual detector chips. On the basis of this fundamental idea, there are a series of further developments which are shown, for example, in U.S. Pat. Nos. 6,479,320 B1 and 6,521,477 B1.
These methods have in common that they result in relatively compact detector chips. On account of the approach employed, these methods have several serious disadvantages, however. First of all, the substrate or the wafer and the lid are typically equal in size. As a result, the flexibility of procuring the lid and the substrate from different sources and manufacturing sites is lost. Lids which may consist of specific materials having precisely defined physical properties are typically not available in the large diameters customary for silicon wafers. This is true, in particular, for microbolometric systems wherein the lid at the same time is the input window for the radiation and thus exhibit a high level of transmittance in the infrared spectral range.
In terms of soldering itself, there is the problem that the wafers are initially adjusted, and after adjustment are placed into a vacuum chamber, where they are then pressed onto one another and soldered. In order not to jeopardize the adjustment with this approach, costly transport and vacuum means may be used.
A further major disadvantage is that in a structure which is bonded and soldered in this manner, it is in each case only the two rear sides of the original wafers that are visible. In this manner, any adjusting marks which may have been placed on the wafer surface and which may be used for sawing up the wafer for singulating using a wafer saw are thus no longer visible without taking additional costly measures. Even if the sawing paths between the detector chips are known, the sawing process itself is highly complicated, since the lid wafer is typically sawn differently from the substrate wafer so that, e.g., bond pads on the substrate wafer will be freely accessible after sawing. Therefore, a smaller surface area generally is to be sawn out from the lid wafer than from the substrate wafer. If the materials of the lid and substrate wafers additionally differ significantly in their compositions or their thicknesses, joint sawing may be impossible since one of the substrates will be destroyed in the process. A further disadvantage relates to the cost of the method particularly if the lid wafer is made of a specific material and is therefore expensive. If the substrate wafer exhibits a poor yield (many defective detector chips), the expensive lid wafer will not be used in the best manner possible, since both intact and defective chips have lids bonded onto them.
A further disadvantage relates to the process of soldering, for which, for example, a solder glass or a low-melting eutectic (for example Au/Sn, 80%/20%, 280°) is used. By means of conventionally deposited solders, the distance between the substrate and the lid wafer cannot simply be adjusted in a reproducible manner since the solder is deposited in various thicknesses. In order to ensure at least a minimum distance, a cavity is often etched into the lid wafer above each chip. The depth of this cavity then predefines a minimum distance from the surface of the substrate wafer. However, this process is costly and entails a series of additional process steps, which moreover complicate deposition of the metal and solder frame on the lid chip. Also, use of soft solder highly restricts the temperature of further processing chips packaged in such a manner.
For connecting CMOS chips, a technique has recently been developed wherein individual chips are deposited on a substrate wafer using a high-speed flip-chip bonder. The publication “Advanced-Chip-to-Wafer Technology: Enabling Technology for Volume Production of 3D System Integration on Wafer Level”, Christoph Scheiring et al., IMAPS 2004, Long Beach, Nov. 14-18, 2004, describes an application which has been developed to electrically interconnect different CMOS chips. For example, the substrate wafer may be manufactured using CMOS logic chips, the lid wafer consists of memory chips. After applying a soldering frame, the lid wafer is sawn up into pieces, and memory chips tested and found to be “functioning” are bonded, as lids, onto chips of the substrate wafer which were also found to be “functioning” in tests. In addition, no soft solder is employed, but the solid liquid interdiffusion (SLID) technique is used. A layer of low-melting metal, e.g. tin (Sn), is placed between top and bottom layers of higher-melting metal, e.g. copper (Cu), and melted at low temperature. The Sn now diffuses upward and downward into the Cu. A higher-melting compound, e.g. Cu3Sn, is formed in the process, which solidifies and connects the two Cu layers.
When building micro-electromechanical systems (MEMS), the SLID technique is frequently used for connecting individual components of the system. SLID is based on that in a suitably selected system consisting of two metals, wherein one metal has a lower melting point than the other metal, a stable alloy may be formed which has a higher melting point than the lower-melting metal. If such metals are contacted with one another and heated to above the melting temperature of the lower-melting metal, the latter will melt and diffuse into the higher-melting metal, so that at the boundary layer an alloy will form which, if the partners have been suitably selected, again exhibits a higher melting temperature than the lower-melting material. If the geometric boundary conditions are suitably selected, the lower-melting metal will fully melt, and a higher-melting and therefore solid alloy, which fully contains the lower-melting metal, will form at the joint.
U.S. Pat. No. 6,793,829 B2 describes that micromechanical components exhibiting the layer sequence of CR/AU/IN/AU/CR may be interconnected in this manner. In this context, what is shown is that a substrate comprising micromechanical components may be connected, by SLID, to a lid consisting, for example, of silicon, glass or ceramic. US patent application 2004/0266048 A1 describes a similar process.